DS626 Datasheet, PDF (7/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
Table 1: MCH_PLBv46_Slave_Burst IO Descriptions (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
P63 Bus2IP_RdReq
User IP O
Active high signal indicating the
initiation of a read operation with the
0
IP. It is asserted for 1 Bus2IP_Clk
during single data beat transactions
and remains high to completion on
burst read operations.
P64 Bus2IP_RdCE(0: see note⁽³⁾)
IP Core O
Active high chip enable bus. Chip
enables are assigned per the user’s
entries in the
C_PLB_ARD_NUM_CE_ARRAY.
0
These chip enables are asserted only
during active read transaction
requests with the target address space
and in conjunction with the
corresponding sub-address within the
space.
P65 Bus2IP_WrCE(0: see note⁽³⁾)
IP Core O
Active high chip enable bus. Chip
enables are assigned per the user’s
entries in the
C_PLB_ARD_NUM_CE_ARRAY.
0
These chip enables are asserted only
during active write transaction
requests with the target address space
and in conjunction with the
corresponding sub-address within the
space.
P66
IP2Bus_Data(0:C_MCH_SIPIF_D
WIDTH-1)
IP Core
I
Input Read Data bus from the user IP.
-
Data is qualified with the assertion of
IP2Bus_Ack signal and the rising edge
of the Bus2IP_Clk.
P67 IP2Bus_AddrAck
IP Core I
Active high signal that advances the
- IPIF Address counter during multiple
data beat transfers.
P68 IP2Bus_WrAck
User IP I
Active high Write Data qualifier. Write
data on the Bus2IP_Data Bus is
-
deemed accepted by the User IP at
the rising edge of the Bus2IP_Clk and
IP2Bus_WrAck asserted high by the
User IP.
P69 IP2Bus_RdAck
User IP I
Active high read data qualifier. Read
data on the IP2Bus_Data Bus is
- deemed valid at the rising edge of
Bus2IP_Clk and the assertion of the
IP2Bus_RdAck signal by the User IP.
P70 IP2Bus_Error
IP Core I
Active high signal indicating the user
IP has encountered an error with the
- requested operation. This signal is
asserted in conjunction with
IP2Bus_Ack.
1. This signal’s function and timing is defined in the IBM® 128-Bit Processor Local Bus Architecture Specification Version 4.6.
2. Log₂ represents a logarithm function of base 2. For example, log₂(1)=0, log₂(2)=1, log₂(4)=2, log₂(8)=3, log₂(16)=4, etc.
3. The size of the Bus2IP_RdCE and the Bus2IP_WrCE buses is the sum of the integer values entered in the
C_PLB_ARD_NUM_CE_ARRAY.
DS626 April 24, 2009
www.xilinx.com
7
Product Specification