DS626 Datasheet, PDF (19/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
X-Ref Target - Figure 6
Clock
XCL_Access_Write(0)
Access_Exists(0)
Access_Read(0)
Access_Control(0)
Access_Data(0.31)
Chnl2IP_CS(0)
Chnl2IP_RNW(0)
Chnl2IP_Addr(0.31)
Chnl2IP_Data(0.31)
XCL_Access_Write(1)
Access_Exists(1)
Access_Read(1)
Access_Control(1)
Access_Data(32.63)
Chnl2IP_CS(1)
Chnl2IP_RNW(1)
Chnl2IP_Addr(32.63)
IP2Chnl_Data(32.63)
IPIC_Addr_Mux_Sel
IPIC_Data_Mux_Sel
Chnl0_Addr0
Chnl0_Data2
Chnl0_Data0
Chnl0_Data1
Chnl0_Addr1
Chnl0_Data3
Chnl0_Addr2
Chnl0_Addr3
Chnl0_Addr 0
Chnl0_Data0
Chnl0_Data1
Chnl0_Data2
Chnl0_Data3
Chnl1_Addr0
Chnl1_Addr0
Chnl 0
Chnl 0
Chnl1_Addr2
Chnl1_Addr1
Chnl1_Addr3
Chnl1_Data1
Chnl1
Chnl1_Data0 Chnl1_Data2
Chnl1
Chnl1_data3
Bus2IP_CS
Bus2IP_Addr
IP2Bus_AddrAck
Bus2IP_RNW
Bus2IP_Data(0.31)
IP2Bus_Data(0.31)
IP2Bus_Ack
Chnl0_Addr1 ^Chnl0_Addr3
Chnl0_Addr0
Chnl0_Addr2
Chnl1_Addr1
Chnl1_Addr0
Chnl1_Addr2
Chnl1_Addr3
Chnl0_Data0
Chnl0_Data1
Chnl0_Data3
Chnl1_Data0
Chnl0_Data2
Chnl1_Data2
Chnl1_Data1 Chnl1_data3
Figure 6: Overlapped Arbitration Timing
If the request winning arbitration is accessing the same external memory bank as the active transaction,
such as Chnl2IP_CS = Bus2IP_CS, the IPIC address mux is switched to this channel during the final
address transfers of the active transaction. This allows the address signals of the next transaction to be
output to the IP and provide continuous address cycles. The IPIC data mux is switched to the new
channel during the final data transfer of the active transaction. However, if the request winning arbitra-
tion is accessing a different external memory bank than the active transaction, such as, Chnl2IP_CS /=
Bus2IP_CS, the both the IPIC address mux and the IPIC data mux are switched to the new channel dur-
ing the final data transfer of the active transaction.
There are no grant signals from the Arbitration Logic to the channel interfaces or the PLB interface. The
IPIC signals of the selected transaction will be multiplexed to the IPIC interface of the IP core and the
responses from the core and will be routed back to the selected channel. The channel interfaces do not
DS626 April 24, 2009
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Product Specification