DS626 Datasheet, PDF (18/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
The arbitration logic is shown in Figure 5.
X-Ref Target - Figure 5
Chn2IP_Addr(n*C_MCH_AWIDTH:
(n+1)*C_MCH_AWIDTH-1)
PLB2IP_Addr_(0:C_
NUM_CHANNELS-1)
Chnl2IP_AddrValid(0:C_
NUM_CHANNELS-1)
PLB2IP_AddrValid
Chn2IP_BE(n*C_MCH_SIPIF_DWIDTH/
8:(n+1)*C_MCH_SIPIF_DWIDTH/8-1)
PLB2IP_BE_(0:C_
SPLB_DWIDTH/8-1)
IP2PLB_AddrAck
IP2Chnl_AddrAck(0:C_
NUM_CHANNELS-1)
Mux/De-Mux
Logic
Addr Mux
Data
De-Mux
Bus2IP_Addr(0:C
_MCH_AWIDTH-1)
Bus2IP_AddrValid
Bus2IP_BE(0:C_
MCH_SIPIF_DWIDTH/8-1)
IP2Bus_AddrAck
Chn2IP_CS(0:m*C_NUM_CHANNELS
PLB2IP_CS_(0:m-1)
Chnl2IP_Data(n*C_MCH_SIPIF_DWIDTH
:(n+1*C_MCH_SIPIF_DWIDTH-1
PLB2IP_Data(0:C_
SPLB_DWIDTH-1)
PLB2IP_RNW
Chn2IP_Burst(0:C_NUM_CHANNELS-1)
8:(n+1)*C_MCH_SIPIF_DWIDTH/8-1)
IP2Chnl_Data(n*C_MCH_SIPIF_DWIDTH:
(n+1)*C_MCH_SIPIF_DWIDTH-1)
IP2OPB_Data(0:C_SPLB_DWIDTH-1)
IP2Chnl_Ack(0:C_NUM_CHANNELS-1)
IP2PLB_Ack
Addr Mux
Bus2IP_CS:(0:m-1)
Bus2IP_Data(0:C
_MCH_SIPIF_DWIDTH-1)
Arbitration Logic
Bus2IP_RNW
Bus2IP_Burst
Addr
Mux
Select
Data
Mux
Select
Data
De-Mux
IP2Bus_Data(0:C
_MCH_SIPIF_DWIDTH-1)
IP2Bus_Ack
Chnl_Req(0*C_NUM_CHANNELS-1)
Chnl_Almost_Done(0:C_NUM_CHANNELS-1)
Chnl2IP_CS(0:m*C_NUM_CHANNELS-1)
PLB2IP_CS(0:m-1)
Figure 5: Arbitration and Mux/De-Mux Logic
DS626_06_031809
The timing of the arbitration cycles and multiplexor control accounts for any registers on the output of
the MUX for the IPIC interface signals that may be necessary to increase F_MAX. The timing relationships
of these signals are shown in Figure 6. The timing diagram is provided only to indicate relative timing
and example responses from an arbitrary IP to demonstrate the overlapped arbitration and control of
the multiplexor/de-multiplexor logic. The diagram is not intended to reflect exact response times of a
particular memory controller and should not be used to determine transaction latency or performance.
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DS626 April 24, 2009
Product Specification