DS626 Datasheet, PDF (14/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
requested is returned first even if that address was not on a cacheline boundary. The subsequent data
words are from sequential addresses wrapping around on the size of the cacheline.
Table 5: ReadData Buffer Signals for Cacheline Read Transfer
MCH ReadData Signal
Value
MCH_ReadData_Control(n)
’0’
timeout or error occurred, data is invalid
’1’
data is valid
MCH_ReadData_Data(n*C_MCH_SIPIF_
DWIDTH: (n+1)*C_MCH_SIPIF_DWIDTH-
1)
X
cacheline data word
control = ’0’
control = ’1’
Figure 2 shows the timing for a XCL cacheline read. The diagram is provided to indicate relative timing
and example responses from some arbitrary IP in order to demonstrate the XCL protocol. It is not
meant to reflect exact response times of a particular memory controller and should not be used to deter-
mine transaction latency or performance.
X-Ref Target - Figure 2
Clock
MCH_Access_Write(1)
MCH_Access_Control(1)
MCH_Access_Data[32:63]
MCH_Access_Full(1)
MCH_ReadData_Read(1)
MCH_ReadData_Control(1)
MCH_ReadData_Data[32:63]
MCH_ReadData_Exists(1)
Chnl1_Addr0
Assertion of MCH_Access_Full(1) depends on parameter setting of MCH(1) buffer size
Chnl1_Data0
Chnl1_Data1
Chnl1_Data2 Chnl1_Data3
Figure 2: XCL Cacheline Read
Driven low by IP to report error condition
DS626_02_031809
XCL Single Write Transfer Protocol (C_XCL_WRITEXFER_ARRAY(n)=1)
The protocol for single write transfers via XCL is as follows:
The cache controller performs two writes into the Access buffer. There is no return status or value. The
formats of these writes are shown in Table 6 and Table 7.
Table 6: Access Buffer Signals for Single Write Transfer - First Write
MCH Access Signal
Value
MCH_Access_Control(n)
’1’
MCH_Access_Data(n*C_MCH_SIPIF_DWIDTH:
(n+1)*C_MCH_SIPIF_DWIDTH-3)
Word aligned address
14
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DS626 April 24, 2009
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