DS626 Datasheet, PDF (6/21 Pages) Xilinx, Inc – Parameterizable depth of channel buffers

Multi-Channel (MCH) PLBv46 Slave Burst (v1.00a)
Table 1: MCH_PLBv46_Slave_Burst IO Descriptions (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
P52 Bus2IP_Reset
IP Core O
Active high reset for use by the User IP.
0 It is a pass through of the SPLB_Rst
input.
P53
Bus2IP_Data(0:C_MCH_SIPIF_D
WIDTH-1)
IP Core
O
Write data bus to the user IP. Write
data is accepted by the IP by assertion
-
of the IP2Bus_Ack signal at the rising
edge of the Bus2IP_Clk (or
unconditionally on the cycle presented
for posted writes).
P54 ^{Bus2IP_Addr(0:C_SPLB_}
AWIDTH-1)
IP Core O
Address bus indicating the desired
- address of the requested read or write
operation.
P55 Bus2IP_RNW
IP Core O
This signal indicates the sense of a
- requested operation with the user IP.
High is a read, low is a write.
P56
Bus2IP_BE(0:(C_MCH_SIPIF_D
WIDTH/8)-1)
IP Core O
Byte enable qualifiers for the
-
requested read or write operation with
the user IP. Bit 0 corresponds to Byte
lane 0, Bit 1 to Byte lane 1, and so on.
P57 Bus2IP_Burst
IP Core O
Active high signal indicating that the
active read or write operation with the
user IP is utilizing bursting protocol.
-
This signal is asserted at the initiation
of a burst transaction with the user IP
and de-asserted at the completion of
the second to last data beat of the
burst data transfer.
P58
Bus2IP_BurstLength(0:log₂(16*C_
MCH_SIPIF_DWIDTH/8))⁽²⁾
User IP
O
This value is an indication of the
number of bytes being requested for
0 transfer aligned with data phase and is
valid when the cycle is of burst type
when Bus2IP_CS=1.
P59
Bus2IP_AddrBurstLength(0:log₂(1
6*C_MCH_SIPIF_DWIDTH/8))
User IP
O
This value is an indication of the
number of bytes being requested for
0 transfer aligned with address phase
and is valid when the cycle is of burst
type when Bus2IP_CS=1.
P60 Bus2IP_AddrBurstCntLoad
User IP O
0
Bus2IP_CS(0:((C_PLB_ARD_AD
P61 DR_RANGE_ARRAY'LENGTH)/2) IP Core O
-1)
Active High chip select bus. Each bit of
the bus corresponds to an entry in the
0
C_ARD_ID_ARRAY. Assertion of a
chip select indicates a active
transaction request to the chip select’s
target address space.
P62 Bus2IP_WrReq
User IP O
Active high signal indicating the
initiation of a write operation with the
0
IP. It is asserted for 1 Bus2IP_Clk
during single data beat transactions
and remains high to completion on
burst write operations
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DS626 April 24, 2009
Product Specification