DS579 Datasheet, PDF (9/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
Allowable Parameter Combinations
The address-range size specified by C_BASEADDR and C_HIGHADDR must be a power of 2, and must be at least
0x40. For example, if C_BASEADDR = 0xE0000000, C_HIGHADDR must be at least = 0xE000003F.
C_PLB_MIDWIDTH depends on C_PLB_NUM_MASTERS. It must be set to the maximum of 1 or the smallest
integer greater than or equal to log₂(C_PLB_NUM_MASTERS).
Below table shows the valid combinations among C_FIFO_DEPTH, C_RD_BURST_SIZE and C_WR_BURST_SIZE.
If C_RD_BURST_SIZE = C_WR_BURST_SIZE and C_FIFO_DEPTH >= 2X of C_RD_BURST_SIZE will give better
performance in terms of latency. The user has the flexibility in choosing these parameters depending on the system
requirements.
Table 3: Allowable FIFO Depth, Read and Write Burst Size Parameters
C_FIFO_DEPTH
C_RD_BURST_SIZE
C_WR_BURST_SIZE
1
1
1
8
8
1
8
8
8
16
8
8
16
8
1
16
16
1
16
16
8
16
16
16
32
8
1
32
8
8
32
16
1
32
16
8
32
16
16
48
8
1
48
8
8
48
16
1
48
16
8
48
16
16
Parameter - Port Dependencies
The dependencies between the XPS Central DMA core design parameters and I/O signals are described in Table 4.
In addition, when certain features are parameterized out of the design, the related logic will no longer be a part of
the design. The unused input signals and related output signals are set to a specified value.
DS579 December 14, 2010
www.xilinx.com
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Product Specification