DS579 Datasheet, PDF (22/23 Pages) Xilinx, Inc – Supports unaligned address transfers

X-Ref Target - Figure 17
LogiCORE IP XPS Central DMA Controller (v2.03a)
MPMC3 XPS CDMA XPS CDMA DUT
MicroBlaze
Processor
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
MDM
DS579_17_041910
Figure 17: Spartan-6 FPGA System the XPS Central DMA core as the DUT
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately 70% and the
I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target F_MAX numbers are shown in Table 19.
Table 19: System Performance
Target FPGA
S3A700 -4
Estimated F_MAX (MHz)
90
V4FX60 -10
100
V5LXT50 -1
120
V6LX130t - 1
150
S6LX45t - 2
100
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
Specification Exceptions
N/A
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
DS579 December 14, 2010
www.xilinx.com
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Product Specification