DS579 Datasheet, PDF (17/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
X-Ref Target - Figure 12
Cycles
PLB_Clk
M_ABus[0:31]
PLB_PAValid
MPLB_MAddrAck
MPLB_MTimeout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
DestinationAddress
10000000
M_size[0:3]
M_BE[0:3]
MPLB_MRdDBus[0:31]
MPLB_MRdDAck
M_RNW
M_rdBurst
MPLB_MRdBTerm
M_wrDBus[0:31]
MPLB_MWrDAck
M_wrBurst
MPLB_MWrBTerm
0000
1111
D0
D0 - The data which was supposed to be transferred from
the Source Address to the Destination Address
DS579_12_041910
Figure 12: Write Time Out for 32-bit Aligned DMA Transfer of Length 8
Design Implementation
Target Technology
The intended target technology is an FPGA listed in the Supported Device Family field of the LogiCORE™ IP Facts
Table.
Device Utilization and Performance Benchmarks
Core Performance
Because the XPS Central DMA Controller core will be used with other design modules in the FPGA, the utilization
and timing numbers reported in this section are estimates only. When this core is combined with other designs in
the system, the utilization of FPGA resources and timing of the XPS Central DMA Controller design will vary from
the results reported here.
DS579 December 14, 2010
www.xilinx.com
17
Product Specification