DS579 Datasheet, PDF (10/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
Table 4: Design Parameter - Port Dependencies
Generic or
Port
Name
Affects
Depends
Relationship Description
Design Parameters
G4
C_MPLB_DWIDTH
P4,P5,P14
-
Affects number of bits in master data bus.
G6
C_SPLB_AWIDTH
P35
Affects number of bits in address bus.
G7
C_SPLB_DWIDTH
P41,P42,
P59
-
Affects number of bits in data bus.
G9
C_SPLB_MID_WIDTH
P46
Affects the width of current master identifier signals
G10
and depends on log₂(C_SPLB_NUM_MASTERS)
with a minimum value of 1.
G10
C_SPLB_NUM_
MASTERS
P62,P63,
P70,P74
-
Affects the width of busy and error signals.
I/O Signals
P3
M_ABUS[0:C_MPLB_
AWIDTH]
-
G5
Width varies with the size of the PLB master address
bus.
P4
M_BE[0:C_MPLB_
DWIDTH/8 - 1]
-
G4
Width varies with the size of the PLB master data bus.
P5
M_wrDBus[0:C_MPLB_
DWIDTH - 1]
-
G4
Width varies with the size of the PLB master data bus.
P14
MPLB_MRdDBus[0:C_
MPLB_DWIDTH - 1]
-
G4
Width varies with the size of the PLB master data bus.
P35
SPLB_ABus[0:C_SPLB
_AWIDTH - 1]
-
G6
Width varies with the size of the PLB address bus.
P41
SPLB_BE[0:C_SPLB_
DWIDTH/8 - 1]
-
G7
Width varies with the size of the PLB data bus.
P42
SPLB_wrDBus[0:C_SP
LB_DWIDTH - 1]
-
G7
Width varies with the size of the PLB data bus.
P46
SPLB_masterID[0:C_
SPLB_MIDWIDTH - 1]
G9
Width varies with the size of the PLB number of
masters.
P59
Sl_rdDBus[0:C_SPLB_
DWIDTH - 1]
-
G7
Width varies with the size of the PLB data bus.
P62
Sl_MWrErr[0:C_SPLB_
NUM_MASTERS - 1]
-
G10
Width varies with the size of the PLB number of
masters.
P63
Sl_MRdErr[0:C_SPLB_
NUM_MASTERS - 1]
-
G10
Width varies with the size of the PLB number of
masters.
P70
Sl_MBusy[0:C_SPLB_
NUM_MASTERS - 1]
-
G10
Width varies with the size of the PLB number of
masters.
P74
Sl_MIRQ[0:C_SPLB_N
UM_MASTERS - 1]
-
G10
Width varies with the size of the PLB number of
masters.
DS579 December 14, 2010
www.xilinx.com
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Product Specification