DS579 Datasheet, PDF (5/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
I/O Signals
The XPS Central DMA Controller I/O signals are listed and described in Table 1. All signals are active high.
Table 1: I/O Signal Description
Port
Signal Name
Interface I/O
Initial
State
Description
PLB Master Interface Signals
P1 MPLB_Clk
P2 MPLB_Rst
P3
M_ABus[0:C_MPLB_
AWIDTH - 1]
P4
M_BE[0:C_MPLB_
DWIDTH/8 - 1]
P5
M_wrDBus[0:C_MPLB_
DWIDTH - 1]
P6 M_request
P7 M_RNW
P8 M_priority[0:1]
P9 M_rdBurst
P10 M_type[0:2]
P11 M_size[0:3]
P12 M_wrBurst
P13 M_MSize[0:1]
P14
MPLB_MRdDBus[0:C_
MPLB_DWIDTH - 1]
P15 MPLB_MBusy
P16 MPLB_MRdErr
P17 MPLB_MWrErr
P18 MPLB_MWrBterm
P19 MPLB_MWrDAck
P20 MPLB_MAddrAck
P21 MPLB_MRdBTerm
P22 MPLB_MRdDAck
P23 MPLB_MRearbitrate
P24 M_TAttribute[0:15]
P25 M_UABus[0:31]
P26 M_lockErr
P27 M_BusLock
P28 M_abort
P29 MPLB_MRdWdAddr[0:3]
PLB
I
PLB
I
PLB
O
PLB
O
PLB
O
PLB
O
PLB
O
PLB
O
PLB
O
PLB
O
PLB
O
PLB
O
PLB
O
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
O
PLB
O
PLB
O
PLB
O
PLB
O
PLB
I
-
PLB master clock
-
PLB master reset
0
Master address bus
0
Master byte enables
0
Master write data bus
0
Master bus request
0
Master read not write
0
Master bus request priority
0
Master burst read transfer indicator
0
Master transfer type
0
Master transfer size
0
Master burst write transfer indicator
0
Master data bus size
-
PLB master read data bus
-
PLB master slave busy indicator
-
PLB master slave read error indicator
-
PLB master slave write error indicator
-
PLB master terminate write burst indicator
-
PLB master write data acknowledge
-
PLB master address acknowledge
-
PLB master terminate read burst indicator
-
PLB master read data acknowledge
-
PLB master bus rearbitrate indicator
0
Master Transfer Attribute bus
0
Master upper address bus
0
Master lock error indicator
0
Master bus lock
0
Master abort bus request indicator
-
PLB master read word address
DS579 December 14, 2010
www.xilinx.com
5
Product Specification