DS579 Datasheet, PDF (14/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
DMA Status Register (DMASR)
The DMA Status Register (DMASR) is shown in Figure 7. It is a read only register addressed at an offset 0x14 from
base address C_BASEADDR. A write to this register has no effect. The bit definitions of this register are as shown
in Table 11..
X-Ref Target - Figure 7
DMABSY
Reserved
01
31
DBE
Figure 7: DMA Status Register (DMASR)
Table 11: DMASR Bit Definitions
Bits
Name
Core
Access
0
DMABSY
Read
1
2 - 31
DBE
Read
Reset
Value
’0’
’0’
Description
DMA Busy:
’0’ = DMA operation is not in progress.
’1’ = DMA operation is in progress.
DMA Bus Error:
’0’ = No DMA bus error.
’1’ = DMA bus error.
Reserved
DS579_07_041910
Interrupt Status Register (ISR)
The Interrupt Status Register (ISR) is shown in Figure 8. It is a read/toggle-on-write register addressed at an offset
0x2C from base address C_BASEADDR. The bit definitions of this register are as shown in Table 12. The interrupt
status bits are set whenever their corresponding condition holds. The corresponding interrupt enable bit set as false
(see Table 13) does not inhibit ISR reporting but does inhibit assertion of the interrupt signal, IP2INTC_Irpt, in
response to the interrupt status bit.
X-Ref Target - Figure 8
Reserved
DE
0
30 31
Figure 8: Interrupt Status Register (ISR)
Table 12: ISR Bit Definitions
Bits
Name Core Access
0 - 29
30
DE
R/TOW
31
DD
R/TOW
Reset
Value
’0’
’0’
Description
Reserved
DMA Error:
’0’ = DMA error has not occurred.
’1’ = DMA error has occurred.
DMA Done:
’0’ = DMA operation is not done.
’1’ = DMA operation is done.
DD
DS579_08_041910
DS579 December 14, 2010
www.xilinx.com
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Product Specification