DS579 Datasheet, PDF (16/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
X-Ref Target - Figure 10
X-Ref Target - Figure 11
Cycles
PLB_Clk
M_ABus[0:31]
PLB_PAValid
MPLB_MAddrAck
M-size[0:3]
M_BE[0:3]
MPLB_MRdDBus[0:31]
MPLB_MRdDAck
M_RNW
M_rdBurst
MPLB_MRdBTerm
M_wrDBus[0:31]
MPLB_MWrDAck
M_wrBurst
MPLB_MWrBTerm
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SourceAddress
30000004
DestinationAddress
40000004
1010
1111
1010
1111
D2
D4
D0
D1
D3
D5
D6
D7
D3
D0
D1
D2
D4 D5 D6 D7
D0 : The first of the 4 bytes of data tranferred from Source
Address(SA) to Destiantion Address(DA)
D1 : The second 4 bytes of data transferred from SA + 0x4 to DA + 0x4
D2 : The third 4 bytes of data transferred from SA + 0x8 to DA + 0x8
D3 : The fourth 4 bytes of data transferred from SA + 0xC to DA + 0xC
D4 : The fifth 4 bytes of data transferred from SA + 0x10 to DA + 0x10
D5 : The sixth 4 bytes of data transferred from SA + 0x14 to DA+ 0x14
D6 : The seventh 4 bytes of data transferred from SA + 0x18 to DA + 0x18
D7 : The last 4 bytes of data transferred from SA + 0x1C to DA + 0x1C
DS579_10_041910
Figure 10: Transaction for 32-bit Aligned DMA Transfer of Length 32
Cycles
PLB_Clk
M_ABus[0:31]
PLB_PAValid
MPLB_MAddrAck
MPLB_MTimeout
M_size[0:3]
M_BE[0:3]
MPLB_MRdDBus[0:31]
MPLB_MRdDAck
M_RNW
M_rdBurst
MPLB_MRdBTerm
M_wrDBus[0:31]
MPLB_MWrDAck
M_wrBurst
MPLB_MWrBTerm
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SourceAddress
10000000
0000
1111
DS579_11_041910
Figure 11: Read Time Out for 32-bit Aligned DMA Transfer of Length 8
DS579 December 14, 2010
www.xilinx.com
16
Product Specification