DS579 Datasheet, PDF (2/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
Functional Description
The block diagram for the XPS Central DMA Controller is shown in Figure 1. The core is comprised of the following
primary modules which are described in the subsequent sections:
• Slave Attachment Module
• Master Attachment Module
• FIFO
• DRE.
X-Ref Target - Figure 1
XPS Central DMA Controller
Slave Attachment Module
IP2INTC_lrpt
PLB
Slave
Interface
PLBv4.6
PLB
Interface
Module
RST
DMACR
SA
DA
LENGTH
DMASR
ISR
IER
Master
Attachment
Module
Read/Write Enable
FIFO DRE
PLB
Master
Interface
PLBv4.6
DS579_01_041910
Figure 1: Block Diagram for the XPS Central DMA Controller
Slave Attachment
The Slave Attachment module performs the following operations:
• Interfaces with the PLB V4.6 using the PLB Interface Module.
• Responds to PLB transactions to read and write the DMA registers.
• Modifies the Source Address, Destination Address, Length, DMA Status and Interrupt Status Registers as a
DMA operation proceeds.
• Generates interrupts based on DMA done and DMA error conditions, detected in the Master Attachment
Module.
Master Attachment
The Master Attachment module performs the following operations:
• Performs read and write transactions as a PLB master to transfer the amount of data specified in the Length
Register from source address to destination address, using bursts where appropriate.
• Detects errors.
• Updates the Source Address, Destination Address, Length and DMA Status Registers during the DMA
transfer.
DS579 December 14, 2010
www.xilinx.com
2
Product Specification