DS579 Datasheet, PDF (3/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
DRE
The DRE (Data Realignment Module) will align the unaligned data before writing in to the FIFO from the source
address or to write in to the destination address from the FIFO.
FIFO
XPS Central DMA Controller contains a 32-bit FIFO:
• Stores the data to be transferred locally.
• The depth of the FIFO can be configured to 1, 16, 32 and 48.
• The FIFO enables the simultaneous read and write transactions based on its vacancy and occupancy.
Controller Operation
The XPS Central DMA Controller operates on the PLB using independent master and slave interfaces. It responds
as a slave when its registers are being read and written. It initiates read and write transactions as a master when a
DMA operation is in progress.
Although it is common to connect the master and slave interfaces to the same bus, it is possible, as shown in
Figure 1, to connect them to different PLB buses, possibly operating at different frequencies. Frequency ratios of 1:1,
2:1 and 1:2 between master and slave bus clocks are supported.
Note: The design accommodates arbitrary clock relationships, including uncorrelated clocks, but the core is specified and
tested for the given ratios only.
The master and slave connections of the XPS Central DMA operate as 32-bit PLB agents. However, either the master
or slave can connect to a PLB with wider data paths (64-bit or 128-bit) and conduct transactions with wider slaves
or masters.
The operation of the XPS Central DMA is initiated by writing values into the following DMA registers. For more
information, see the Register Descriptions.
• Source Address register (SA): The source address for the transfer is written into this register.
• Destination Address register (DA): The destination address for the transfer is written into this register.
• DMA Control Register (DMACR): The parameters of the DMA transfer are controlled by setting the following
values in this register.
• Source Increment (SINC): SINC should be set to ’0’, if and only if the Source Address register is written
with a keyhole address such that a single address is associated with a sequence of data.
Note: An example of a keyhole address is a memory mapped FIFO that maps as an element at a single address but
can consume or produce an endless sequence of data. A variation on a keyhole address is a wide keyhole where a
number of consecutive addresses map to the element. When SINC = ’0’, XPS Central DMA will perform all read
transactions to the same address. It is the responsibility of the corresponding slave to impose a keyhole behavior. For
bursts, this implies that the slave will not increment the keyhole address during the burst or will make the keyhole at least
as wide as the burst size. It is not feasible to use SINC = ’0’ with a non-keyhole slave such as a memory. Even though
the DMA Controller would deliver a non-incremented address during the address phase of PLB transactions, the
memory would increment it during bursts. (See also DINC, which is subject to the same considerations when set to ’0’.)
• If the source address should increment for each data transferred, SINC should set to ’1’.
• Destination Increment (DINC): DINC should be set to ’0’ if and only if the Destination Address is written
with a keyhole address such that a single address is associated with a sequence of data.
Note: See the note for SINC = ‘0’ above. The case DINC = ‘0’ has the same considerations except for the destination
address.
• If the destination address should increment for each data transferred, DINC should set to ’1’.
DS579 December 14, 2010
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Product Specification