DS579 Datasheet, PDF (7/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
Table 1: I/O Signal Description (Cont’d)
Port
Signal Name
Interface I/O
Initial
State
P60 Sl_addrAck
PLB
O
0
P61 Sl_SSize[0:1]
PLB
O
0
P62
Sl_MWrErr[0:C_SPLB_NUM_
MASTERS - 1]
PLB
O
0
P63
Sl_MRdErr[0:C_SPLB_NUM_
MASTERS - 1]
PLB
O
0
P64 Sl_wait
PLB
O
0
P65 Sl_rearbitrate
PLB
O
0
P66 Sl_wrDAck
PLB
O
0
P67 Sl_wrComp
PLB
O
0
P68 Sl_rdDAck
PLB
O
0
P69 Sl_rdComp
PLB
O
0
P70
Sl_MBusy[0:C_SPLB_NUM_
MASTERS - 1]
PLB
O
0
P71 Sl_wrBTerm
PLB
O
0
P72 Sl_rdWdAddr[0:3]
PLB
O
0
P73 Sl_rdBTerm
PLB
O
0
P74
Sl_MIRQ[0:C_SPLB_NUM_
MASTERS - 1]
PLB
O
0
System Signals
P75 IP2INTC_Irpt
System
O
0
Description
Slave address acknowledge
Slave data bus size
Slave write error indicator
Slave read error indicator
Slave wait indicator
Slave rearbitrate bus indicator
Slave write data acknowledge
Slave write transfer complete indicator
Slave read data acknowledge
Slave read transfer complete indicator
Slave busy indicator
Slave terminate write burst transfer
Slave read word address
Slave terminate read burst transfer
Slave interrupt indicator
DMA Interrupt
Design Parameters
To allow the user to create a XPS Central DMA Controller that is uniquely tailored for the user’s system, certain
features are parameterizable in the XPS Central DMA Controller design. This allows the user to have a design that
utilizes only the resources required by the system and runs at the best possible performance. The features that are
parameterizable in the XPS Central DMA core are as shown in Table 2.
DS579 December 14, 2010
www.xilinx.com
7
Product Specification