DS579 Datasheet, PDF (1/23 Pages) Xilinx, Inc – Supports unaligned address transfers

DS579 December 14, 2010
LogiCORE IP XPS Central DMA
Controller (v2.03a)
Product Specification
Introduction
The XPS Central DMA Controller provides simple
Direct Memory Access (DMA) services to peripherals
and memory devices on the PLB. The controller
transfers a programmable quantity of data from a
source address to a destination address without
processor intervention.
Features
• Connects as a 32-bit master/slave on PLB V4.6
buses of 32, 64 or 128 bits
• Provides a single physical channel of Direct
Memory Access between a source address and a
destination address
• Provides programmable registers for source
address, destination address and transfer length
• Parameterizable local FIFO depth and burst length
• Supports different clock domains for Master and
Slave interfaces
• The source address and destination address can be
arbitrarily aligned (down to the byte)
• Supports overlapped PLB read/write transfers
which will give better performance
• Supports unaligned address transfers
• Supports setting up of source and destination
addresses as incrementing or fixed (keyhole)
• Supports PLB burst transfers
LogiCORE™ IP Facts Table
Core Specifics
Spartan®-3, Spartan-3E, Spartan-3A,
Supported
Spartan-6, Spartan-3A DSP, Automotive
Device Family⁽¹⁾ Spartan-3/3A/3A DSP/ 3E, Virtex®-4, Virtex-4Q,
Virtex-4QV, Virtex-5/5FX, Virtex-6/6CX
Supported User
Interfaces
PLBv46
Resources
Block RAMS
LUTs
Slices
FFs
For Virtex-5 FPGA, see Table 14, for Virtex-5
FPGA, see Table 15, for Spartan-3E, see
Table 16, for Virtex-6 FPGA, see Table 17. and
for Spartan-6 FPGA, see Table 18.
Provided with Core
Documentation
Product Specification
Design Files
VHDL
Example Design
Not Provided
Test Bench
Not Provided
Constraints File
Not Provided
Simulation
Model
N/A
Tested Design Tools
Design Entry
Tools
Platform Studio
Simulation
Mentor Graphic ModelSim v6.5c and above
Synthesis Tools
XST
Support
Provided by Xilinx, Inc.
Notes:
1. For a complete listing of supported devices, see the release
notes for this core.
© Copyright 2007-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United
States and other countries. The PowerPC name and logo are registeed trademarks of IBM Corp. and are used under license. All other trademarks are the property
of their respective owners.
DS579 December 14, 2010
www.xilinx.com
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Product Specification