DS579 Datasheet, PDF (4/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
• LENGTH register (LENGTH): The number of bytes to transfer is written into this register. Writing to this
register is the event that starts the DMA operation, so it must be done last. (Refer to Table 10 for more
information on this register)
The data transfer starts by reading data from the source address into an internal FIFO followed by the transfer of
data from the FIFO to the destination address. This repeats until all the data is moved. The DMA Status Registers
get updated as the DMA operation progresses.
While it is moving data as the bus master, the XPS Central DMA Controller attempts to move data efficiently. It
utilizes burst transactions where possible.
The status of the DMA operation is available in the DMA Status Register (DMASR). The DMABSY bit equal to ’1’
represents that a DMA operation is underway. When equal to ’0’, it represents the completion of a DMA transfer.
Alternatively, the DMA Done (DD) interrupt can be used to detect when a DMA operation is complete.
If an error condition is detected during a bus transfer, the DMA operation will be aborted at its current point of
progress. The error is reported through the DMA Error (DE) interrupt condition and the DMA Bus Error (DBE)
status bit.
Interrupt and Error Condition Descriptions
DMA Interrupt Conditions
Interrupt conditions, which are established by the occurrence of interrupt events, are stored in the Interrupt Status
Register of the channel (see Table 12). Interrupt conditions can be reported, cleared and enabled.
• Reporting: Port signal IP2INTC_Irpt is active if and only if either of the interrupt conditions occurs.
• Clearing: Active interrupt conditions are cleared by writing a value to the Interrupt Status Register with a 1 in
the bit position to be cleared.
• Enabling: Interrupts are enabled by setting the corresponding bit in the Interrupt Enable Register. (see
Table 13)
Error Conditions
A DMA operation proceeds until it is complete or until it is aborted due to an error condition detected on the bus.
If completion is due to an error, the corresponding DMA BUS Error (DBE) bit of the DMA Status Register (DMASR)
will be set. Additionally, the DMA Error (DE) interrupt condition will become active. The final values of LENGTH,
SA and DA will reflect the partial completion status of the DMA operation, taking into account that unwritten data
will be flushed out by resetting the internal FIFO.
DS579 December 14, 2010
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Product Specification