DS579 Datasheet, PDF (15/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) is shown in Figure 9. It is a read/write register addressed at an offset 0x30 from
base address C_BASEADDR. The bit definitions of this register are as shown in Table 13. These bits inhibit assertion
of the IP2INTC_Irpt signal in response to the corresponding interrupt status bit (see Table 12).
X-Ref Target - Figure 9
Reserved
DEIE
0
30 31
Figure 9: Interrupt Enable Register (IER)
DDIE
DS579_09_041910
Table 13: IER Bit Definitions
Bits
Name
Core
Access
Reset
Value
0 - 29
30
DEIE
R/W
’0’
31
DDIE
R/W
’0’
Description
Reserved
DMA Error Interrupt Enable: Interrupt enable bit for DMA error.
’0’ = IP2INTC_Irpt will not assert in response to DMA Error interrupt status.
’1’ = IP2INTC_Irpt will assert in response to DMA Error interrupt status.
DMA Done Interrupt Enable: Interrupt enable bit for DMA done.
’0’ = IP2INTC_Irpt will not assert in response to DMA Done interrupt status.
’1’ = IP2INTC_Irpt will assert in response to DMA Done interrupt status.
Timing Diagrams
The following timing diagrams illustrate the XPS Central DMA Controller operation for various read and write
transactions of different lengths.
1. Read and write transactions of a 32-bit aligned DMA transfer of length 32 bytes are shown in Figure 10.
2. Read and write transactions of a time-out case in a 32-bit aligned DMA transfer of length 8 bytes are shown in
Figure 11 and Figure 12.
DS579 December 14, 2010
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Product Specification