DS579 Datasheet, PDF (13/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
Destination Address Register (DA)
The Destination Address Register (DA) is shown in Figure 5. It is a read/write register addressed at an offset 0xC
from base address C_BASEADDR.The bit definitions of this register are as shown in Table 9.
X-Ref Target - Figure 5
SA
0
31
DS579_05_041910
Figure 5: Destination Address Register (DA)
Table 9: DA Register Bit Definitions
Bits
Name
Core
Access
Reset
Value
Description
0 - 31 DA
R/W
Destination Address: Destination address for the current DMA operation. When
DINC = ’1’, as data is moved to the destination address, this register updates to track
0 the current destination address. When DINC = ’0’, the destination address remains
constant at the programmed value. (See also the DINC field of the DMA Control
Register.)
Length Register (LENGTH)
Length Register (LENGTH) is shown in Figure 6. It is a read/write register addressed at an offset 0x10 from base
address C_BASEADDR. The bit definitions of this register are as shown in Table 10.
X-Ref Target - Figure 6
LENGTH
0
31
DS579_06_041910
Figure 6: Length Register (LENGTH)
Table 10: LENGTH Register Bit Definitions
Bits
Name
Core Reset
Access Value
Description
0 - 31 LENGTH ⁽¹⁾ R/W
Length of the DMA Transfer: The DMA operation starts when the number of
bytes to be transferred from source to destination is written to the Length
Register. Therefore, this register is written only after the DMA Control register,
0
the Source Address and the Destination Address registers have been written
with their desired values and any other setup is complete. As bytes are
successfully written to the destination, the Length Register decrements to reflect
the number of bytes remaining to be transferred. The Length Register will be zero
after a successful DMA operation.
1. If the written value is not a multiple of DSIZE, the transfer is a mix of byte as well as a word transfers. For example, if the Length
Register is programmed to ten bytes, the XPS Central DMA Controller will transfer the two bytes using the byte enables as a single
transfer. The remaining eight bytes will be transferred as two data word burst. The final value of the Length Register will be zero.
DS579 December 14, 2010
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Product Specification