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DS579 Datasheet, PDF (12/23 Pages) Xilinx, Inc – Supports unaligned address transfers
LogiCORE IP XPS Central DMA Controller (v2.03a)
DMA Control Register (DMACR)
The DMA Control Register (DMACR) is shown in Figure 3. It is a read/write register addressed at an offset 0x4
from base address C_BASEADDR. The bit definitions of this register are as shown in Table 7.
X-Ref Target - Figure 3
SINC
Reserved
0 12
31
DINC
Figure 3: DMA Control Register (DMACR)
DS579_03_041910
Table 7: DMACR Bit Definitions
Bits
Name
Core
Access
Reset
Value
0
SINC
R/W
’1’
1
DINC
R/W
’0’
2 - 31
Description
Source Increment: Increment the source address by the number of source bytes
read.
’1’ = Increment the source address.
’0’ = Do not increment the source address. SINC = ’0’ is allowed if and only if the
Source Address register is written with a keyhole address. See also the An example
of a keyhole address note on page 3.
Destination Increment: Increment the destination address by the number of bytes
written in to the destination.
’1’ = Increment the destination address
’0’ = Do not increment the destination address. DINC = ’0’ is allowed if and only if
the Destination Address register is written with a keyhole address. See also The
case DINC = ‘0’ note on page 3.
Reserved
Source Address Register (SA)
The Source Address Register (SA) is shown in Figure 4. It is a read/write register addressed at an offset 0x8 from
base address C_BASEADDR. The bit definitions of this register are as shown in Table 8.
X-Ref Target - Figure 4
SA
0
31
DS579_04_041910
Figure 4: Source Address Register (SA)
Table 8: SA Register Bit Definitions
Bits
Name
Core
Access
Reset
Value
Description
0 - 31 SA
R/W
Source Address: Source address for the current DMA operation. When SINC =
0
’1’, as data is moved from the source address, this register updates to track the
current source address. When SINC = ’0’, the source address remains constant at
the programmed value. (See also the SINC field of the DMA Control Register).
DS579 December 14, 2010
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Product Specification