DS579 Datasheet, PDF (20/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
Table 18 shows the XPS Central DMA Controller resource utilization for various parameter combinations measured
with Spartan-6 FPGA as the device under test (DUT).
Table 18: Performance and Resource Utilization Benchmarks on the Spartan-6 FPGA (xc6slx45-2-fgg484)
Parameter Values
Device Resources
Performance
F_Max (MHz)
8
8
8
289
564
727
101
16
16
16
299
566
730
100
48
16
16
305
577
720
110
16
16
1
290
553
660
111
32
16
8
315
616
766
112
48
16
8
310
590
737
115
System Performance
To measure the system performance (F_MAX) of this core, this core was added the Device Under Test (DUT) to a
Virtex-4 FPGA system as shown in Figure 13, a Virtex-5 FPGA system as shown in Figure 14, a Spartan-3A FPGA
system as shown in Figure 15, a Spartan-6 FPGA system as shown in Figure 16, and a Virtex-6 FPGA system as
shown in Figure 17 as.
Because the XPS Central DMA core will be used with other design modules in the FPGA, the utilization and timing
numbers reported in this section are estimates only. When the XPS Central DMA core is combined with other
designs in the system, the utilization of FPGA resources and timing of the XPS Central DMA design will vary from
the results reported here.
X-Ref Target - Figure 13
PLBV46
PLBV46
MPMC5
XPS CDMA XPS CDMA
Device Under
Test (DUT)
IPLB1 DPLB1
DPLB0
PowerPC 405
Processor ^IPLB0
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
DS579_13_041910
Figure 13: Virtex-4 FX FPGA System the XPS Central DMA core as the DUT
DS579 December 14, 2010
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Product Specification