DS579 Datasheet, PDF (8/23 Pages) Xilinx, Inc – Supports unaligned address transfers

LogiCORE IP XPS Central DMA Controller (v2.03a)
Table 2: Design Parameters
Generic Feature/Description Parameter Name
Allowable Values
Default
Value
VHDL Type
System Parameter
G1 Target FPGA family
C_FAMILY
aspartan3, spartan3,
spartan3a, spartan3e,
aspartan3a, aspartan3e,
aspartan3a,
aspartan3adsp, spartan6,
virtex4, qrvirtex4, qvirtex4,
virtex5, virtex6
virtex5
string
PLB Parameters
G2
XPS Central DMA
Controller Base Address
C_BASEADDR
Valid Address⁽¹⁾
None⁽²⁾ std_logic_vector
G3
XPS Central DMA
Controller High Address
C_HIGHADDR
Valid Address⁽¹⁾
None⁽²⁾ std_logic_vector
G4 PLB master data width C_MPLB_DWIDTH 32,64,128
32
integer
G5
PLB master address
width
C_MPLB_AWIDTH 32
32
integer
G6 PLB address width
C_SPLB_AWIDTH 32
32
integer
G7 PLB data width
C_SPLB_DWIDTH 32, 64, 128
32
integer
Selects point-to-point or
shared PLB topology
G8 0 = Shared Bus Topology C_SPLB_P2P
0
1 = Point-to-Point Bus
Topology
0
integer
G9
PLB Master ID Bus
Width
C_SPLB_MID_
WIDTH
log₂(C_SPLB_
NUM_MASTERS) with a
minimum value of 1
1
integer
G10
Number of PLB Masters
C_SPLB_NUM_MAS
TERS
1 - 16
1
integer
G11
Width of the Slave Data C_SPLB_NATIVE_
Bus
DWIDTH
32
32
integer
G12 Burst support
C_SPLB_SUPPORT_
BURSTS
0
0
integer
G13
Width of the Master Data C_MPLB_NATIVE_
Bus
DWIDTH
32
32
integer
G14 FIFO Depth⁽³⁾
G15 Read Burst Size⁽⁴⁾
G16 Write Burst Size⁽⁴⁾
XPS Central DMA Controller Feature
C_FIFO_DEPTH
1, 8, 16, 32, 48
C_RD_BURST_SIZE 1, 8, 16
C_WR_BURST_SIZE 1, 8, 16
16
integer
16
integer
16
integer
Notes:
1. C_BASEADDR must be a multiple of the address-range size, where the size is C_HIGHADDR - C_BASEADDR + 1.
2. No default value will be specified to insure that the actual value is set.
3. FIFO Depth should be greater than or equal to the Read Burst Size and Write Burst Size
4. Read Burst Size should be greater than or equal to the Write burst Size
DS579 December 14, 2010
www.xilinx.com
8
Product Specification