W25Q256FVBIF-TR Datasheet, PDF (99/108 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q256FV
AC Electrical Characteristics (cont’d)
DESCRIPTION
SPEC
SYMBOL ALT
MIN TYP
MAX
UNIT
/HOLD to Output Low-Z
/HOLD to Output High-Z
Write Protect Setup Time Before /CS Low
Write Protect Hold Time After /CS High
/CS High to Power-down Mode
/CS High to Standby Mode without ID Read
/CS High to Standby Mode with ID Read
/CS High to next Instruction after Suspend
/CS High to next Instruction after Reset
/RESET pin Low period to reset the device
Write Status Register Time
tHHQX⁽²⁾
tLZ
7
ns
tHLQZ⁽²⁾
tHZ
12
ns
tWHSL⁽³⁾
20
ns
tSHWL⁽³⁾
100
ns
tDP⁽²⁾
3
µs
tRES1⁽²⁾
3
µs
tRES2⁽²⁾
1.8
µs
tSUS⁽²⁾
20
µs
tSUS⁽²⁾
30
µs
tRST⁽²⁾⁽⁵⁾
1
µs
tW
10
15
ms
Byte Program Time (First Byte)
tBP1(4)
30
50
µs
Additional Byte Program Time (After First Byte)
tBP2(4)
2.5
12
µs
Page Program Time
tPP
W25Q256FvxxIG
Sector Erase Time (4KB)
W25Q256FVxxIQ
tSE
W25Q256FVxxIF
Block Erase Time (32KB)
tBE1
Block Erase Time (64KB)
tBE2
Chip Erase Time
tCE
0.7
3
ms
100
400
ms
45
120
1,600
ms
150
2,000
ms
80
400
s
Notes:
1.Clock high + Clock low must be less than or equal to 1/fC.
2.Value guaranteed by design and/or characterization, not 100% tested in production.
3.Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1).
4.For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number
of bytes programmed.
5.It’s possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to ensure
reliable operation.
6.4-bytes address alignment for QPI/Quad Read
- 98 -
Publication Release Date: February 11, 2015
Preliminary – Revision H