W25Q256FVBIF-TR Datasheet, PDF (14/108 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q256FV
6.1.6 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q256FV operation to be
paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where
the SPI data and clock signals are shared with other devices. For example, consider if the page buffer
was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD
function can save the state of the instruction and the data in the buffer so programming can resume
where it left off once the bus is available again. The /HOLD function is only available for standard SPI and
Dual SPI operation, not during Quad SPI. The Quad Enable Bit QE in Status Register-2 is used to
determine if the pin is used as /HOLD pin or data I/O pin. When QE=0 (factory default), the pin is /HOLD,
when QE=1, the pin will become an I/O pin, /HOLD function is no longer available.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate
on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the
rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD
condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data
Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip
Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid
resetting the internal logic state of the device.
6.1.7 Software Reset & Hardware /RESET pin
The W25Q256FV can be reset to the initial power-on state by a software Reset sequence, either in SPI
mode or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) &
Reset (99h). If the command sequence is successfully accepted, the device will take approximately 30uS
(tRST) to reset. No command will be accepted during the reset period.
For the WSON-8 and TFBGA package types, W25Q256FV can also be configured to utilize a hardware
/RESET pin. The HOLD/RST bit in the Status Register-3 is the configuration bit for /HOLD pin function or
RESET pin function. When HOLD/RST=0 (factory default), the pin acts as a /HOLD pin as described
above; when HOLD/RST=1, the pin acts as a /RESET pin. Drive the /RESET pin low for a minimum
period of ~1us (tRESET*) will reset the device to its initial power-on state. Any on-going Program/Erase
operation will be interrupted and data corruption may happen. While /RESET is low, the device will not
accept any command input.
If QE bit is set to 1, the /HOLD or /RESET function will be disabled, the pin will become one of the four
data I/O pins.
Hardware /RESET pin has the highest priority among all the input signals. Drive /RESET low for a
minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the
status of other SPI signals (/CS, CLK, IOs, /WP and/or /HOLD).
Note: While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device,
a 1us minimum is recommended to ensure reliable operation.
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