W25Q256FVBIF-TR Datasheet, PDF (65/108 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q256FV
8.2.26 Quad Input Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously
erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can
improve performance for PROM Programmer and applications that have slow clock speeds <5MHz.
Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction
since the inherent page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable (QE) bit in Status Register-2 must be set to 1. A Write
Enable instruction must be executed before the device will accept the Quad Page Program instruction
(Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the
instruction code “32h” followed by a 24/32-bit address (A23/A31-A0) and at least one data byte, into the
IO pins. The /CS pin must be held low for the entire length of the instruction while data is being sent to the
device. All other functions of Quad Page Program are identical to standard Page Program. The Quad
Page Program instruction sequence is shown in Figure 30.
/CS
CLK
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (32h)
24-Bit Address
IO₀
23 22 21
3210
*
IO₁
IO₂
IO₃
* ^{= MSB}
/CS
CLK
IO₀
31 32 33 34 35 36 37
Byte 1 Byte 2 Byte 3
0404040
Byte
253
40
Byte
254
40
Byte
255
40
Byte
256
40
IO₁
515151
51515151
IO₂
626262
62626262
IO₃
737373
***
73737373
****
Figure 30. Quad Input Page Program Instruction (SPI Mode only)
32-Bit Address is required when the device is operating in 4-Byte Address Mode
Mode 3
Mode 0
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Publication Release Date: February 11, 2015
Preliminary – Revision H