W25Q256FVBIF-TR Datasheet, PDF (13/108 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q256FV
critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins
become bidirectional I/O pins: IO0 and IO1.
6.1.3 Quad SPI Instructions
The W25Q256FV supports Quad SPI operation when using instructions such as “Fast Read Quad Output
(6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O
(E3h)”. These instructions allow data to be transferred to or from the device four to six times the rate of
ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and
random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI
bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and
the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-
volatile Quad Enable bit (QE) in Status Register-2 to be set.
6.1.4 QPI Instructions
The W25Q256FV supports Quad Peripheral Interface (QPI) operations only when the device is switched
from Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI
protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight
serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial
clocks are required. This can significantly reduce the SPI instruction overhead and improve system
performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only
one mode can be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to
switch between these two modes. Upon power-up or after a software reset using “Reset (99h)” instruction,
the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile
Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and
DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3
respectively. See Figure 3 for the device operation modes.
6.1.5 3-Byte / 4-Byte Address Modes
The W25Q256FV provides two Address Modes that can be used to specify any byte of data in the
memory array. The 3-Byte Address Mode is backward compatible to older generations of serial flash
memory that only support up to 128M-bit data. To address the 256M-bit or more data in 3-Byte Address
Mode, Extended Address Register must be used in addition to the 3-Byte addresses.
4-Byte Address Mode is designed to support Serial Flash Memory devices from 256M-bit to 32G-bit. The
extended Address Register is not necessary when the 4-Byte Address Mode is enabled.
Upon power up, the W25Q256FV can operate in either 3-Byte Address Mode or 4-Byte Address Mode,
depending on the Non-Volatile Status Register Bit ADP (S17) setting. If ADP=0, the device will operate in
3-Byte Address Mode; if ADP=1, the device will operate in 4-Byte Address Mode. The factory default
value for ADP is 0.
To switch between the 3-Byte or 4-Byte Address Modes, “Enter 4-Byte Mode (B7h)” or “Exit 4-Byte Mode
(E9h)” instructions must be used. The current address mode is indicated by the Status Register Bit ADS
(S16).
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Publication Release Date: February 11, 2015
Preliminary – Revision H