W25Q256FVBIF-TR Datasheet, PDF (67/108 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q256FV
8.2.28 32KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “52h” followed a 24/32-bit block address (A23/A31-A0). The Block Erase
instruction sequence is shown in Figure 32a & 32b.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase
instruction will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of
the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Block Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (CMP, TB, BP3,
BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
/CS
CLK
DI
(IO₀)
DO
(IO₁)
Mode 3
0
Mode 0
* ^{= MSB}
123456789
29 30 31
Instruction (52h)
24-Bit Address
23 22
*
High Impedance
210
Mode 3
Mode 0
Figure 32a. 32KB Block Erase Instruction (SPI Mode)
32-Bit Address is required when the device is operating in 4-Byte Address Mode
/CS
CLK
IO₀
Mode 3
Mode 0
01234567
Instruction
52h
A23-16
20 16
A15-8
12 8
A7-0
40
Mode 3
Mode 0
IO₁
21 17 13 9 5 1
IO₂
22 18 14 10 6 2
IO₃
23 19 15 11 7 3
Figure 32b. 32KB Block Erase Instruction (QPI Mode)
32-Bit Address is required when the device is operating in 4-Byte Address Mode
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Publication Release Date: February 11, 2015
Preliminary – Revision H