W25Q256FVBIF-TR Datasheet, PDF (84/108 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q256FV
8.2.43 Read Security Registers (48h)
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data
bytes to be sequentially read from one of the four security registers. The instruction is initiated by driving
the /CS pin low and then shifting the instruction code “48h” followed by a 24/32-bit address (A23/A31-A0)
and eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the
CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out
on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is
automatically incremented to the next byte address after each byte of data is shifted out. Once the byte
address reaches the last byte of the register (byte address FFh), it will reset to address 00h, the first byte
of the register, and continue to increment. The instruction is completed by driving /CS high. The Read
Security Register instruction sequence is shown in Figure 47. If a Read Security Register instruction is
issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will
not have any effects on the current cycle. The Read Security Register instruction allows clock rates from
D.C. to a maximum of FR (see AC Electrical Characteristics).
ADDRESS
Security Register #1
Security Register #2
Security Register #3
{A23/A31}-16
00h
00h
00h
A15-12
0001
0010
0011
A11-8
0000
0000
0000
A7-0
Byte Address
Byte Address
Byte Address
/CS
CLK
DI
(IO₀)
DO
(IO₁)
/CS
CLK
DI
(IO₀)
DO
(IO₁)
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Instruction (48h)
24-Bit Address
23 22 21
*
High Impedance
3210
* ^{= MSB}
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Byte
076543210
High Impedance
Data Out 1
Data Out 2
76543210765432107
*
*
Figure 47. Read Security Registers Instruction (SPI Mode only)
32-Bit Address is required when the device is operating in 4-Byte Address Mode
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