W25Q256FVBIF-TR Datasheet, PDF (20/108 Pages) Winbond – 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q256FV
7.1.13 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable
The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1,
DRV0
Driver
Strength
0, 0
100%
0, 1
75%
1, 0
50%
1, 1
25%(default)
7.1.14 /HOLD or /RESET Pin Function (HOLD/RST) – Volatile/Non-Volatile Writable
The HOLD/RST bit is used to determine whether /HOLD or /RESET function should be implemented on
the hardware pin. When HOLD/RST=0 (factory default), the pin acts as /HOLD; when HOLD/RST=1, the
pin acts as /RESET. However, /HOLD or /RESET functions are only available when QE=0. If QE is set to
1, the /HOLD and /RESET functions are disabled, the pin acts as a dedicated data I/O pin.
7.1.15 Reserved Bits – Non Functional
There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be
written as “0”, but there will not be any effects.
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