W9751G8JB Datasheet, PDF (9/86 Pages) Winbond – 16M  4 BANKS  8 BIT DDR2 SDRAM

W9751G8JB
7. FUNCTIONAL DESCRIPTION
7.1 Power-up and Initialization Sequence
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures
other than those specified may result in undefined operation. The following sequence is required for
Power-up and Initialization.
1. Apply power and attempt to maintain CKE below 0.2 × VDDQ and ODT^*1 at a LOW state (all other
inputs may be undefined.) Either one of the following sequence is required for Power-up.
A. The VDD voltage ramp time must be no greater than 200 mS from when VDD ramps from 300
mV to VDD min; and during the VDD voltage ramp, |VDD -VDDQ| ≤ 0.3 volts.
 VDD, VDDL and VDDQ are driven from a single power converter output
 VTT is limited to 0.95V max
 VREF^*2 tracks VDDQ/2
 VDDQ ≥ VREF must be met at all times
B. Voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid
DRAM latch-up. During the ramping of the supply voltages, VDD ≥ VDDL ≥ VDDQ must be
maintained and is applicable to both AC and DC levels until the ramping of the supply voltages
is complete.
 Apply VDD/VDDL^*3 before or at the same time as VDDQ
 Apply VDDQ^*4 before or at the same time as VTT
 VREF^*2 tracks VDDQ/2
 VDDQ ≥ VREF must be met at all times.
2. Start Clock and maintain stable condition for 200 µ S (min.).
3. After stable power and clock (CLK, CLK ), apply NOP or Deselect and take CKE HIGH.
4. Wait minimum of 400 nS then issue precharge all command. NOP or Deselect applied during 400
nS period.
5. Issue an EMRS command to EMR (2). (To issue EMRS command to EMR (2), provide LOW to
BA0, HIGH to BA1.)
6. Issue an EMRS command to EMR (3). (To issue EMRS command to EMR (3), provide HIGH to
BA0 and BA1.)
7. Issue an EMRS command to EMR (1) to enable DLL. (To issue DLL Enable command, provide
LOW to A0, HIGH to BA0 and LOW to BA1 and A13. And A9=A8=A7=LOW must be used when
issuing this command.)
8. Issue a Mode Register Set command for DLL reset. (To issue DLL Reset command, provide HIGH
to A8 and LOW to BA0-BA1 and A13.)
9. Issue a precharge all command.
10. Issue 2 or more Auto Refresh commands.
11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating
parameters without resetting the DLL.)
12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment).
If OCD calibration is not used, EMRS to EMR (1) to set OCD Calibration Default
(A9=A8=A7=HIGH) followed by EMRS to EMR (1) to exit OCD Calibration Mode
(A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).
13. The DDR2 SDRAM is now ready for normal operation.
Publication Release Date: Oct. 12, 2010
-9-
Revision A01