W9751G8JB Datasheet, PDF (5/86 Pages) Winbond – 16M  4 BANKS  8 BIT DDR2 SDRAM

W9751G8JB
3. KEY PARAMETERS
SYM.
SPEED GRADE
Bin(CL-tRCD-tRP)
Part Number Extension
@CL = 7
@CL = 6
tCK(avg) Average clock period
@CL = 5
@CL = 4
@CL = 3
tRCD
tRP
tRC
tRAS
IDD0
IDD1
IDD4R
IDD4W
IDD5B
IDD6
IDD7
Active to Read/Write Command Delay Time
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
Operating current
Operation current (Single bank)
Operating burst read current
Operating burst write current
Burst refresh current
Self refresh current (TCASE ≤ 85°C)
Operating bank interleave read current
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
DDR2-1066
7-7-7
-18
1.875 nS
7.5 nS
2.5 nS
7.5 nS
3 nS
7.5 nS
3.75 nS
7.5 nS


13.125 nS
13.125 nS
53.125 nS
40 nS
65 mA
70 mA
120 mA
125 mA
85 mA
6 mA
135 mA
DDR2-800
5-5-5/6-6-6
-25/25I


2.5 nS
8 nS
2.5 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
12.5 nS
12.5 nS
52.5 nS
40 nS
55 mA
62 mA
85 mA
110 mA
80 mA
6 mA
120 mA
DDR2-667
5-5-5
-3




3 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
15 nS
15 nS
55 nS
40 nS
55 mA
60 mA
80 mA
105 mA
80 mA
6 mA
110 mA
Publication Release Date: Oct. 12, 2010
-5-
Revision A01