W9751G8JB Datasheet, PDF (67/86 Pages) Winbond – 16M  4 BANKS  8 BIT DDR2 SDRAM

W9751G8JB
10. TIMING WAVEFORMS
10.1 Command Input Timing
tCK
CLK
CLK
CS
tCK
tIS
tIH
tCH
tCL
RAS
CAS
WE
A0~A13
BA0,1
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
Refer to the Command Truth Table
10.2 Timing of the CLK Signals
CLK
CLK
CLK
CLK
tCH
tCL
tT
tT
tCK
VX
VX
VX
VIH
VIH(AC)
VIL(AC)
VIL
VIH
VIL
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Publication Release Date: Oct. 12, 2010
Revision A01