W9751G8JB Datasheet, PDF (7/86 Pages) Winbond – 16M  4 BANKS  8 BIT DDR2 SDRAM

W9751G8JB
5. BALL DESCRIPTION
BALL NUMBER SYMBOL
H8,H3,H7,J2,J8,J3,
J7,K2,K8,K3,H2,K7,
L2,L8
A0−A13
G2,G3
BA0−BA1
C8,C2,D7,D3,D1,D9,
B1,B9
DQ0−DQ7
F9
ODT
B7,A8
DQS, DQS
FUNCTION
DESCRIPTION
Address
Provide the row address for active commands, and the column
address and Auto-precharge bit for Read/Write commands to select
one location out of the memory array in the respective bank.
Row address: A0−A13.
Column address: A0−A9. (A10 is used for Auto-precharge)
Bank Select
BA0−BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines if the
mode register or one of the extended mode registers is to be
accessed during a MRS or EMRS command cycle.
Data Input
/ Output
Bi-directional data bus.
On Die Termination ODT (registered HIGH) enables termination resistance internal to the
Control
DDR2 SDRAM.
Data Strobe /
Differential Read
Data Strobe
Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write
data. DQS is only used when differential data strobe mode is
enabled via the control bit at EMR (1) [A10] = 0.
All commands are masked when CS is registered
G8
CS
Chip Select
HIGH. CS provides for external Rank selection on systems with
multiple Ranks. CS is considered part of the command code.
F7,G7,F3
B3
A2
RAS , CAS ,
WE
Command Inputs
RAS , CAS and WE (along with CS ) define the command being
entered.
DM/RDQS
Input Data Mask/
Read Data Strobe
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a Write
access. DM is sampled on both edges of DQS. Although DM is input
only, the DM loading matches the DQ and DQS loading. When
RDQS is enabled, RDQS is output with read data only and is ignored
during write data. RDQS is enabled by EMR (1) [A11] = 1. If RDQS is
enabled, the DM function is disabled.
NU/ RDQS
Not Use/Differential
Read Data Strobe
RDQS is only used when RDQS is enabled and differential data
strobe mode is enabled. If differential data strobe mode is disabled
via the control bit at EMR (1) [A10] = 1, then ball A2 and A8 are not
used.
E8,F8
F2
E2
A1,E9,H9,L1
A3,E3,J1,K9
A9,C1,C3,C7,C9
A7,B2,B8,D2,D8
G1,L3,L7
E1
E7
CLK, CLK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
VDDL
VSSDL
Differential Clock
Inputs
Clock Enable
Reference Voltage
Power Supply
Ground
DQ Power Supply
DQ Ground
No Connection
DLL Power Supply
DLL Ground
CLK and CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK
and negative edge of CLK . Output (read) data is referenced to the
crossings of CLK and CLK (both directions of crossing).
CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM.
VREF is reference voltage for inputs.
Power Supply: 1.8V ±0.1V.
Ground.
DQ Power Supply: 1.8V ±0.1V.
DQ Ground. Isolated on the device for improved noise immunity.
No connection.
DLL Power Supply: 1.8V ±0.1V.
DLL Ground.
Publication Release Date: Oct. 12, 2010
-7-
Revision A01