W9751G8JB Datasheet, PDF (11/86 Pages) Winbond – 16M  4 BANKS  8 BIT DDR2 SDRAM

W9751G8JB
SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2
does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must
be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the
table for specific codes.
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Field
0
0 0*¹ PD
WR
DLL TM
CAS Latency
BT
Burst Length
Mode Register
A8 DLL Reset
0
No
1
Yes
BA1 BA0
0
0
0
1
1
0
1
1
MRS mode
MR
EMR (1)
EMR (2)
EMR (3)
A12
Active power down exit time
0
Fast exit (use tXARD)
1
Slow exit (use tXARDS)
A7
Mode
0
Normal
1
Test
Write recovery for Auto-precharge
A11 A10 A9
WR *²
0
0
0
Reserved
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
A3
Burst Type
0
Sequential
1
Interleave
Burst Length
A2 A1 A0 BL
0
1
0
4
0
1
1
8
CAS Latency
A6 A5 A4 Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Note:
1. A13 reserved for future use and must be set to "0" when programming the MR.
2. WR (write recovery for Auto-precharge) min is determined by tCK(avg) max and WR max is determined by tCK(avg) min.
WR[cycles] = RU{ tWR[nS] / tCK(avg)[nS] }, where RU stands for round up. The mode register must be programmed to this
value. This is also used with tRP to determine tDAL
Figure 2 – Mode Register Set (MRS)
7.2.2 Extend Mode Register Set Commands (EMRS)
7.2.2.1 Extend Mode Register Set Command (1), EMR (1)
( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L, A0 to A13 = Register data)
The extended mode register (1) stores the data for enabling or disabling the DLL, output driver
strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended
mode register (1) is not defined, therefore the extended mode register (1) must be programmed during
initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register (1). The mode register set command
cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (1).
Extended mode register (1) contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. A0 is used for
DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the
additive latency, A[9:7] are used for OCD control, A10 is used for DQS disable and A11 is used for
RDQS enable. A2 and A6 are used for ODT setting.
- 11 -
Publication Release Date: Oct. 12, 2010
Revision A01