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| W9751G8JB Datasheet, PDF (57/86 Pages) Winbond – 16M 4 BANKS 8 BIT DDR2 SDRAM | |||
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W9751G8JB
CLK
CLK
VDDQ
tIS
tIH
tIS
tIH
VIH(ac)min
VREF to AC
region
VIH(dc)min
nominal
line
VREF(dc)
tangent
line
tangent
line
VIL(dc)max
VIL(ac)max
nominal
line
VSS
ÎTF
VREF to AC
region
ÎTR
Setup Slew Rate tangent line[VIH(ac)min - VREF(dc)]
Rising Signal =
ÎTR
Setup Slew Rate tangent line[VREF(dc) - VIL(ac)max]
Falling Signal =
ÎTF
Figure 21 â Illustration of tangent line for tIS
- 57 -
Publication Release Date: Oct. 12, 2010
Revision A01
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