W9751G8JB Datasheet, PDF (46/86 Pages) Winbond – 16M  4 BANKS  8 BIT DDR2 SDRAM

W9751G8JB
AC Characteristics and Operating Condition for -25/25I/-3 speed grades, continued
SYM.
SPEED GRADE
Bin(CL-tRCD-tRP)
DDR2-800
(-25/25I)
5-5-5/6-6-6
PARAMETER
MIN.
MAX.
tWPRE Write preamble
0.35

tWPST Write postamble
0.4
0.6
tRPRE Read preamble
0.9
1.1
tRPST Read postamble
0.4
0.6
tDS(base) DQ and DM input setup time
50

tDH(base) DQ and DM input hold time
125

tDS(ref) DQ and DM input setup time
250

tDH(ref) DQ and DM input hold time
tDIPW
tHZ
DQ and DM input pulse width for each
input
Data-out high-impedance time from
CLK/ CLK
250
0.35



tAC,max
DDR2-667
(-3)
5-5-5
MIN.
MAX.
0.35

0.4
0.6
0.9
1.1
0.4
0.6
100

175

300

300

0.35


tAC,max
UNITS²⁵ NOTES
tCK(avg)
tCK(avg) 12
tCK(avg) 14,36
tCK(avg) 14,37
pS
16,27,29,
41,42,44
pS
17,27,29,
41,42,44
pS
16,27,29,
41,42,44
pS
17,27,29,
41,42,44
tCK(avg)
pS 15,35
DQS/ DQS -low-impedance time from
tLZ(DQS)
CLK/ CLK
tAC,min
tAC,max
tAC,min
tAC,max
pS 15,35
tLZ(DQ) _{DQ low-impedance time from CLK/ CLK} 2 x tAC,min tAC,max 2 x tAC,min tAC,max
pS 15,35
tHP Clock half pulse width
Min.
Min.
(tCH(abs),

(tCH(abs),

tCL(abs))
tCL(abs))
pS
32
tQHS Data hold skew factor

300

340
pS
33
tQH DQ/DQS output hold time from DQS
tHP - tQHS

tHP - tQHS

pS
34
tXSNR Exit Self Refresh to a non-Read command tRFC + 10

tRFC + 10

nS
23
tXSRD Exit Self Refresh to a Read command
200

200

nCK
tXP
Exit precharge power down to any
command
2

2

nCK
tXARD Exit active power down to Read command
2

2

nCK
18
Exit active power down to Read command
tXARDS
8 - AL

7 - AL

nCK 18,19
(slow exit, lower power)
tAOND ODT turn-on delay
2
2
2
2
nCK
20
tAON ODT turn-on
tAC,min tAC,max + 0.7 tAC,min tAC,max + 0.7 nS
20,35
tAONPD ODT turn-on (Power Down mode)
tAC,min + 2
2 x tCK(avg) +
tAC,max + 1
tAC,min + 2
2 x tCK(avg) +
tAC,max + 1
nS
tAOFD ODT turn-off delay
2.5
2.5
2.5
2.5
nCK 21,39
tAOF ODT turn-off
tAC,min tAC,max + 0.6 tAC,min tAC,max + 0.6 nS 21,38,39
tAOFPD ODT turn-off (Power Down mode)
tAC,min + 2
2.5 x tCK(avg)
+ tAC,max + 1
tAC,min + 2
2.5 x tCK(avg)
+ tAC,max + 1
nS
tANPD ODT to power down Entry Latency
3

3

nCK
tAXPD ODT Power Down Exit Latency
8
8
nCK
tMRD Mode Register Set command cycle time
2

2

nCK
tMOD MRS command to ODT update delay
0
12
0
12
nS
23
tOIT OCD Drive mode output delay
0
12
0
12
nS
23
tDELAY
Minimum time clocks remain ON after
CKE asynchronously drops LOW
tIS+tCK(avg)+
tIH

tIS+tCK(avg)+
tIH

nS
22
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Publication Release Date: Oct. 12, 2010
Revision A01