W9751G8JB Datasheet, PDF (8/86 Pages) Winbond – 16M  4 BANKS  8 BIT DDR2 SDRAM

6. BLOCK DIAGRAM
W9751G8JB
CLK
CLK
CKE
CS
RAS
CAS
WE
DLL
CLOCK
BUFFER
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10
A0
A9
A11
A12
A13
BA1
BA0
ADDRESS
BUFFER
MODE
REGISTER
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #0
SENSE AMPLIFIER
PREFETCH REGISTER
DATA CONTROL
CIRCUIT
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
DQ
BUFFER
COLUMN DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
NOTE: The cell array configuration is 16384 * 1024 * 8
ODT
ODT
CONTROL
DQ0
|
DQ7
DQS
DQS
RDQS
RDQS
DM
Publication Release Date: Oct. 12, 2010
-8-
Revision A01