W9751G8JB Datasheet, PDF (35/86 Pages) Winbond – 16M  4 BANKS  8 BIT DDR2 SDRAM

W9751G8JB
Function Truth Table, continued
CURRENT
STATE
CS
RAS CAS WE
ADDRESS
COMMAND
ACTION
NOTES
H
X
X
X
X
DSL
NOP-> Bank active after tWR
L
H
H
H
X
NOP
NOP-> Bank active after tWR
L
H
L
H ^{BA, CA, A10} READ/READA
ILLEGAL
1
Write
L
H
L
L BA, CA, A10 WRIT/WRITA
New write
Recovering _L
L
H
H BA, RA
ACT
ILLEGAL
1
L
L
H
L BA, A10
PRE/PREA
ILLEGAL
1
L
L
L
H
X
AREF/SELF
L
L
L
L ^Op-Code
MRS/EMRS
ILLEGAL
ILLEGAL
H
X
X
X
X
DSL
NOP-> Precharge after tWR
L
H
H
H
X
NOP
NOP-> Precharge after tWR
L
H
L
H ^{BA, CA, A10} READ/READA
ILLEGAL
1
Write
Recovering ^L
H
L
L BA, CA, A10 WRIT/WRITA
ILLEGAL
1
with Auto-
L
L
H
H BA, RA
ACT
ILLEGAL
1
precharge
L
L
H
L BA, A10
PRE/PREA
ILLEGAL
1
L
L
L
H
X
AREF/SELF
L
L
L
L ^Op-Code
MRS/EMRS
ILLEGAL
ILLEGAL
H
X
X
X
X
DSL
NOP-> Idle after tRC
L
H
H
H
X
NOP
L
H
L
H ^{BA, CA, A10} READ/READA
L
H
L
L BA, CA, A10 WRIT/WRITA
Refreshing
L
L
H
H BA, RA
ACT
L
L
H
L BA, A10
PRE/PREA
L
L
L
H
X
AREF/SELF
L
L
L
L Op-Code
MRS/EMRS
NOP-> Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
H
X
X
X
X
DSL
L
H
H
H
X
NOP
L
H
L
H BA, CA, A10 _READ/READA
Mode
L
H
L
L BA, CA, A10 _WRIT/WRITA
Register
Accessing
L
L
H
H BA, RA
ACT
L
L
H
L BA, A10
PRE/PREA
L
L
L
H
X
AREF/SELF
L
L
L
L Op-Code
MRS/EMRS
NOP-> Idle after tMRD
NOP-> Idle after tMRD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Notes:
1. This command may be issued for other banks, depending on the state of the banks.
2. All banks must be in "IDLE".
3. Read or Write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8. Burst read/write can
only be interrupted by another read/write with 4 bit burst boundary. Any other case of read/write interrupt is not allowed.
Remark: H = High level, L = Low level, X = High or Low level (Don‟t Care), V = Valid data.
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Publication Release Date: Oct. 12, 2010
Revision A01