W9751G8JB Datasheet, PDF(47/86 Page) Winbond – 16M  4 BANKS  8 BIT DDR2 SDRAM

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

W9751G8JB Datasheet, PDF (47/86 Pages) Winbond – 16M  4 BANKS  8 BIT DDR2 SDRAM

◁

W9751G8JB

Notes:

1. All voltages are referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage

levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ODT is

disabled for all measurements that are not ODT-specific.

3. AC timing reference load:

VDDQ

Output

DUT

DQS

Timing

25Î©

reference

point

VTT = VDDQ/2

Figure 16 â AC timing reference load

4. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min)

have been satisfied.

5. If refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid READ

can be executed.

6. This is an optional feature. For detailed information, please refer to âoperating temperature conditionâ section 9.2 in this data

sheet.

7. tCKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the

valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not

transition from its valid level during the time period of tIS + 2 x tCK + tIH.

8. A minimum of two clocks (2 *nCK) is required irrespective of operating frequency.

9. tWTR is at least two clocks (2 * nCK) independent of operation frequency.

10. There are two sets of values listed for Command/Address input setup time: tIS(base) and tIS(ref). The tIS(ref) value (for

reference only) is equivalent to the baseline value of tIS(base) at VREF when the slew rate is 1.0 V/nS. The baseline value

tIS(base) is the JEDEC defined value, referenced from the input signal crossing at the VIH(ac) level for a rising signal and

VIL(ac) for a falling signal applied to the device under test. See Figure 17. If the Command/Address slew rate is not equal to

1.0 V/nS, then the baseline values must be derated by adding the values from table of tIS/tIH derating values for DDR2-667,

DDR2-800 and DDR2-1066 (page 55).

CLK

Logic levels

tIS(base) tIH(base)

VREF levels

tIS(ref)

tIH(ref)

tIS(ref)

tIH(ref)

Figure 17 â Differential input waveform timing â tIS and tIH

VDDQ

VIH(ac) min

VIH(dc) min

VREF(dc)

VIL(dc) max

VIL(ac) max

VSS

- 47 -

Publication Release Date: Oct. 12, 2010

Revision A01

▷