W83627THF_06 Datasheet, PDF (84/142 Pages) Winbond – Winbond LPC I/O

W83627THF/W83627THG
CR23 (Default 0x00)
Bit 7 - 1 : RESERVED.
Bit 0
: IPD (Immediate Power Down).
down mode immediately.
When set to 1, it will put the whole chip into power
CR24 (Default 0s110s1sb)
Bit 7 : Reserved
Bit 6 : CLKSEL
= 0 The clock input on Pin 18 should be 24 Mhz.
= 1 The clock input on Pin 18 should be 48 Mhz.
The corresponding power-on setting pin is SOUTB (pin 83).
Bit 5 - 3 : Reserved
Bit 2 : ENKBC
= 0 KBC is disabled after hardware reset.
= 1 KBC is enabled after hardware reset.
This bit is read only, and set/reset by power-on setting pin. The corresponding power-
on setting pin is SOUTA (pin 54).
Bit 1 : Reserved. Must be 1.
Bit 0 : PNPCSV
= 0 The Compatible PnP address select registers have default values.
= 1 The Compatible PnP address select registers have no default value.
When trying to make a change to this bit, new value of PNPCVS must be complementary to the old
one to make an effective change. For example, the user must set PNPCSV to 0 first and then
reset it to 1 to reset these PnP registers if the present value of PNPCSV is 1. The corresponding
power-on setting pin is NDTRA (pin 52).
CR25 (Default 0x00)
Bit 7 - 6 : Reserved
Bit 5 : URBTRI
Bit 4 : URATRI
Bit 3 : PRTTRI
Bit 2 - 1 : Reserved
Bit 0 : FDCTRI.
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Publication Release Date: September 26, 2006
Revision 1.2