W83627THF_06 Datasheet, PDF (81/142 Pages) Winbond – Winbond LPC I/O

W83627THF/W83627THG
registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration
registers against accidental accesses.
The configuration registers can be reset to their default or hardware settings only by a cold reset (pin
MR = 1). A warm reset will not affect the configuration registers.
6.1.2 Extended Functions Enable Registers (EFERs)
After a power-on reset, the W83627THF enters the default operating mode. Before the W83627THF
enters the extended function mode, a specific value must be programmed into the Extended Function
Enable Register (EFER) so that the extended function register can be accessed. The Extended
Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are
2Eh or 4Eh (as described in previous section).
6.1.3 Extended Function Index Registers (EFIRs), Extended Function Data
Registers(EFDRs)
After the extended function mode is entered, the Extended Function Index Register (EFIR) must be
loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration
Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function
Data Register (EFDR). The EFIRs are write-only registers with port address 2Eh or 4Eh (as described
in section 12.2.1) on PC/AT systems, the EFDRs are read/write registers with port address 2Fh or 4Fh
(as described in section 9.2.1) on PC/AT systems.
6.2 Configuration Sequence
To program W83627THF configuration registers, the following configuration sequence must be
followed:
(1). Enter the extended function mode
(2). Configure the configuration registers
(3). Exit the extended function mode
6.2.1 Enter the extended function mode
To place the chip into the extended function mode, two successive writes of 0x87 must be applied to
Extended Function Enable Registers(EFERs, i.e. 2Eh or 4Eh).
6.2.2 Configuration the configuration registers
The chip selects the logical device and activates the desired logical devices through Extended
Function Index Register(EFIR) and Extended Function Data Register(EFDR). EFIR is located at the
same address as EFER, and EFDR is located at address (EFIR+1).
First, write the Logical Device Number (i.e.,0x07) to the EFIR and then write the number of the desired
logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not required.
Secondly, write the address of the desired configuration register within the logical device to the EFIR
and then write (or read) the desired configuration register through EFDR.
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