TH58NVG1S3AFT Datasheet, PDF (5/32 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

AC TEST CONDITIONS
PARAMETER
Input level
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
TH58NVG1S3AFT05
CONDITION
2.4 V, 0.4 V
3ns
1.5 V, 1.5 V
1.5 V, 1.5 V
C_L (100 pF)  1 TTL
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta 0 to 70ˆ, V_CC 2.7V ~ 3.6V)
SYMBOL
PARAMETER
MIN
t_PROG
Average Programming Time

Number of Programming Cycles on Same Page
N

(per 512+16 bytes)
t_BERASE Block Erasing Time

(1) Refer to Application Note (12) toward the end of this document.
TYP.
200

2
MAX
700
2
4
UNIT NOTES
Ps
(1)
ms
2003-05-19A 5/32