TH58NVG1S3AFT Datasheet, PDF (24/32 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

APPLICATION NOTES AND COMMENTS
TH58NVG1S3AFT05
(1) Power-on/off sequence:
The timing sequence shown in Figure 15 is necessary for power-on/off sequence.
The device internal initialization start after the power supply reaches appropriate level in power on
sequence. During the initialization the device Ready/Busy signal outputs Busy state as shown in the
Figure-15. In this time period, the acceptable commands are FFh or 70h.
The WP signal is useful for protecting against data corruption at power-on/off.
0V
CE , WE , RE
CLE, ALE
2.7V
2.5V
V_CC
don’t
care
V_IL
WP
1ms max
100µs max
Ready/Busy
invalid
V_IH
Operation
don’t
care
V_IL
don’t
care
Figure 15. Power-on/off Sequence
(2) Status after power-on
The following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF
Reset
Figure 16.
(3) Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3
is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4) Restriction of command while Busy state
During Busy state, do not input any command except 70H, and FFH.
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