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TH58NVG1S3AFT Datasheet, PDF (27/32 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS | |||
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TH58NVG1S3AFT05
(10) Note regarding the WP signal
The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follows:
Enable Programming
WE
DIN
80
10
WP
RY / BY
tWW (100 ns MIN)
Disable Programming
WE
DIN
80
10
WP
RY / BY
tWW (100 ns MIN)
Enable Erasing
WE
DIN
60
D0
WP
RY / BY
tWW (100 ns MIN)
Disable Erasing
WE
DIN
60
WP
RY / BY
tWW (100 ns MIN)
D0
2003-05-19A 27/32
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