TH58NVG1S3AFT Datasheet, PDF (20/32 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TH58NVG1S3AFT05
ID Read
The device contains ID code which identify the device type, the manufacturer, and some features of the device.
The ID codes can be read out under the following timing conditions:
CLE
CE
t_CEA
WE
ALE
t_ALEA
RE
t_REAID
I/O
90H
00H
98H
DAH
Note1
ID Read
command
Address
00
Maker code Device code
Note2
For the specifications of the access times t_REAID and t_ALEA refer to the AC Characteristics.
Figure 13. ID Read timing
Note3
Note1 : 81H or 01H
Note2 : 95H or 15H
Note3 : 44H or C4H
Table 6. Code table
Descripton
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
1^st Data
2^nd Data
Maker Code
Device Code
1
0
0
1
1
0
0
0
1
1
0
1
1
0
1
0
3^rd Data
Chip Number, Cell Type,
0 or 1 0
0
0
0
0
0
1
PGM Page, Write Cache
4^th Data
Page Size, Block Size,
0 or 1 0
0
1
0
1
0
1
Redundant Size, Organization
5^th Data
Plane Number, Plane Size 0 or 1 1
0
0
0
1
0
0
Hex Data
98H
DAH
81H or 01H
95H or 15H
44H or C4H
3^rd Data
Internal Chip Number
Cell Type
Number of simultaneously
programmed pages
Reserved 1
Reserved 2
Descripton
1
2
4
8
2 level cell
4 level cell
8 level cell
16 level cell
1
2
4
8
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0 or 1
2003-05-19A 20/32