TH58NVG1S3AFT Datasheet, PDF (2/32 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

BLOCK DIAGRAM
I/O1
to
I/O8
CE
CLE
ALE
WE
RE
WP
RY / BY
I/O
Control
circuit
Logic
control
RY / BY
TH58NVG1S3AFT05
Status register
Address register
Command register
Control
circuit
V_CC V_SS
Column buffer
Column decoder
Data register
Sense amp
Memory
cell array
HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
V_CC
V_IN
V_I/O
P_D
T_SOLDER
T_STG
T_OPR
Power Supply Voltage
Input Voltage
Input /Output Voltage
Power Dissipation
Soldering Temperature (10s)
Storage Temperature
Operating Temperature
VALUE
0.6 to 4.6
0.6 to 4.6
0.6 V to V_CC  0.3 V (ʽ 4.6 V)
0.3
260
-55 to 150
0 to 70
CAPACITANCE *(Ta 25°C, f 1 MHz)
SYMB0L
PARAMETER
CONDITION
MIN
C_IN
Input
V_IN 0 V

C_OUT
Output
V_OUT 0 V

* * This parameter is periodically sampled and is not tested for every device.
MAX
20
20
UNIT
V
V
V
W
°C
°C
°C
UNIT
pF
pF
xThe products described in this document are subject to the foreign exchange and foreign trade laws.
xThe information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
xThe information contained herein is subject to change without notice.
2003-05-19A 2/32