TH58NVG1S3AFT Datasheet, PDF (1/32 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TH58NVG1S3AFT05
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2GBIT (256M u 8BITS) CMOS NAND E²PROM
DESCRIPTION
The TH58NVG1S3A is a single 3.3-V 2G-bit (2,214,592,512 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E²PROM) organized as (2048+64) bytes x 64 pages x 2048 blocks.
The device has a 2112-byte static registers which allow program and read data to be transferred
between the register and the memory cell array in 2112-byte increments. The Erase operation is
implemented in a single block unit (128 Kbytes + 4Kbytes: 2112 bytes x 64 pages).
The TH58NVG1S3A is a serial-type memory device which utilizes the I/O pins for both address and data
input / output as well as for command inputs. The Erase and Program operations are automatically
executed making the device most suitable for applications such as solid-state file storage, voice
recording, image file memory for still cameras and other systems which require high-density non-
volatile memory data storage.
FEATURES
x Organization
Memory cell allay 2112 u 64K u 8 u 2
Register
2112 u 8
Page size
2112bytes
Block size
(128K  4K) bytes
x Modes
Read㧘Reset㧘Auto Page Program
Auto Block Erase㧘Status Read
x Mode control
Serial input㧛output
Command control
x Powersupply
VCC 2.7 V to 3.6 V
x Program/Erase Cycles 1E5 Cycles(With ECC)
x Access time
Cell array to register 25 Psmax
Serial Read Cycle
50 ns min
x Operating current
Read (50 ns cycle)
10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby
50 PA max
x Package
TSOP I 48-P-1220-0.50
(Weight : 0.53 g typ.)
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
NC 1
NC 2
NC 3
NC 4
NC 5
GND 6
RY/BY 7
RE 8
CE ⁹
NC 10
NC 11
VCC 12
VSS 13
NC 14
NC 15
CLE 16
ALE 17
WE 18
WP ¹⁹
NC 20
NC 21
NC 22
NC 23
NC 24
48 NC
47 NC
46 NC
45 NC
44 I/O8
43 I/O7
42 I/O6
41 I/O5
40 NC
39 NC
38 NC
37 VCC
36 VSS
35 NC
34 NC
33 NC
32 I/O4
31 I/O3
30 I/O2
29 I/O1
28 NC
27 NC
26 NC
25 NC
I/O1 to I/O8
CE
WE
RE
CLE
ALE
WP
RY / BY
GND
V_CC
V_SS
I/O port
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready / Busy
Ground Input
Power supply
Ground
000707EBA1
xTOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
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Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
xThe TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
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the customer’s own risk.
2003-05-19A 1/32