TH58NVG1S3AFT Datasheet, PDF (4/32 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TH58NVG1S3AFT05
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta 0 to 70ˆ, V_CC 2.7V ~ 3.6V)
SYMBOL
PARAMETER
t_CLS
t_CLH
t_CS
t_CH
t_WP
t_ALS
t_ALH
t_DS
t_DH
t_WC
t_WH
t_WW
t_RR
t_RW
t_RP
t_RC
t_REA
t_CEA
t_CLEA
t_ALEA
t_REAID
t_OH
t_RHZ
t_CHZ
t_REH
t_IR
t_RSTO
t_CSTO
t_CLSTO
t_RHW
t_WHC
t_WHR
t_R
t_WB
t_RST
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Ready to WE Falling Edge
Read Pulse Width
Read Cycle Time
RE Access Time (Serial Data Access)
CE Access Time
CLE Access Time
ALE Access Time
RE Access Time (ID Read)
Data Output Hold Time
RE High to Output High Impedance
CE High to Output High Impedance
RE High Hold Time
Output-High-impedance-to- RE Falling Edge
RE Access Time (Status Read)
CE Access Time (Status Read)
CLE Access Time (Status Read)
RE High to WE Low
WE High to CE Low
WE High to RE Low
Memory Cell Array to Starting Address
WE High to Busy
Device Reset Time (Read/Program/Erase)
MIN
MAX
UNIT NOTES
0

ns
10

ns
0

ns
10

ns
25

ns
0

ns
10

ns
20

ns
10

ns
50

ns
15

ns
100

ns
20

ns
20

ns
35

ns
50

ns

35
ns

45
ns

45
ns

45
ns

35
ns
10

ns

30
ns

20
ns
15

ns
0

ns

35
ns

45
ns

45
ns
30

ns
30

ns
30

ns

25
Ps

200
ns

6/10/500
Ps
2003-05-19A 4/32