TH58NVG1S3AFT Datasheet, PDF (29/32 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TH58NVG1S3AFT05
(12) Several programming cycles on the same page (Partial Page Program)
A page can be divided into up to 8 segments as follows :-
Data area (column address 0 to 2047)
: 512 bytes x 4 segments
1^st segment: column address 0 to 511
2^nd segment: column address 512 to 1023
3^rd segment: column address 1024 to 1535
4^th segment: column address 1536 to 2047
Redundant area (column address 2048 to 2111) : 16 bytes x 4 segments
1^st segment: column address 2048 to 2063
2^nd segment: column address 2064 to 2079
3^rd segment: column address 2080 to 2095
4^th segment: column address 2096 to 2111
. Each segment can be programmed individually as follows:
1st programming
Data Pattern 1
2nd programming
All 1s
Data Pattern 2
All 1s
All 1s
8th programming
All 1s
Data Pattern 8
Result
Data Pattern 1
Data Pattern 2
Data Pattern 8
Figure 24.
Note: The input data for unprogrammed or previously programmed page segments must be "1"
(i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all “1”).
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