TH58NVG1S3AFT Datasheet, PDF (18/32 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TH58NVG1S3AFT05
DEVICE OPERATION
Read Mode
Read mode is set when "00H" and “30H” commands are issued to the Command register. Between the
commands, start address for the Read mode need to be issued. Refer to Figure 3 below for sequence and the
block diagram (Refer to the detailed timing chart.).
CLE
CE
WE
ALE
RE
RY / BY
Column Address M Page Address N
Busy
I/O
00H
30H
M M+1 M+2
Select page
N
Start-address input
M
2111
Cell array
Figure 3. Read mode (1) operation
Page Address N
A data transfer operation from the cell array to the register
starts on the rising edge of WE in the 30h command input cycle
(after the address information has been latched). The device will
be in Busy state during this transfer period.
After the transfer period the device returns to Ready state.
Serial data can be output synchronously with the RE clock from
the start address designated in the address input cycle.
Random Column Address Change in Read Cycle
CLE
CE
WE
ALE
RE
RY / BY
00H
I/O
Busy
30H
Col. M
M M+1 M+2 M+3 ^05H
E0H _M’ M’+1 _{M’+2 M’+3 M’+4}
Col. M
Page N
Start-address input
M
M’
Select page
N
Page N
Start from Col. M
Col. M’
Page N
Start from Col. M’
Cell array
In the serial data out from the register, the column address
can be changed by inputting the column address with 05h and
E0h commands.
The data are read out in serial from the column address which
is input to the device by 05h and E0h commands with /RE clock.
Figure 4. Random Column Address Change in Serial Read
2003-05-19A 18/32